Title :
An Improved Single Event Resistive-Hardening Technique for CMOS Static RAMS
Author :
Johnson, Richard L., Jr. ; Diehl, Sherra E.
Author_Institution :
North Carolina State University Department of Electrical and Computer Engineering Box 7911 Raleigh, NC 27695-7911
Abstract :
A technique that will improve RAM cell performance while maintaining single event upset immunity has been identified. The resistor-hardening configuration combines cross-coupled gate resistors and a pair of resistors used to isolate the miore sensitive devices (those not fabricated in wells). Improvements in RAM cell write time and critical charge are discussed as well as the impact of this technique on the cell´s noise miargin.
Keywords :
CMOS process; CMOS technology; Circuits; Computer simulation; Feedback; Radiation hardening; Random access memory; Read-write memory; Resistors; Single event upset;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.1986.4334679
