Title :
Time Loss Through Gating of Asynchronous Logic Signal Pulses
Author_Institution :
Semiconductor Products Division, Motorola Inc., Phoenix, Ariz.
Abstract :
The gating of asynchronous signals causes logical errors. It is possible to reduce the frequency of these errors, but the price paid is a severe loss of time and extra cost in hardware.
Keywords :
Chaos; Clocks; Costs; Frequency synchronization; Hardware; Logic; Metastasis; Sampled data systems;
Journal_Title :
Electronic Computers, IEEE Transactions on
DOI :
10.1109/PGEC.1966.264407
