(MI)/SUP 2/L: multiinput-multioutput integrated injection logic

The (MI)/SUP 2/L structure will be discussed, which is a combination of CHL/CHIL and I/SUP 2/L, taking advantage of ion implantation. It provides improved speed-power product and functional density compared to conventional I/SUP 2/L schemes. The gate consists of a lateral n-p-n transistor with intermediate collectors and a Schottky inverter. The device fabrication is fully compatible with standard bipolar processes for analog circuits. The approach is applied to a standard bipolar process of 6 /spl mu/m epi thickness and 35 V breakdown voltage. The results obtained are a minimum power-delay product of 0.07 pJ and a minimum delay of 17 ns at 0.38 pJ. The improved device parameters, packing density, and design flexibility are discussed with the experimental results of test circuits, including a D-type frequency divider and MS flip-flop.