A versatile ECL multiplexer IC for the Gbit/s range

A new approach to digital multiplexing for communication systems operating in the Gbit/s range is presented. With a single function, monolithically integrated in the established silicon bipolar process, many operations required by the communication system´s multiplex equipment are achieved at data rates of up to 3 Gbits/s. The IC is a four-channel multiplexer designed to interface readily with ECL families. Demonstrations of the ICs performance include pseudorandom pattern generation by multiplexing ECL inputs up to 2 Gbits/s, demultiplexing into ECL registers at 1 Gbits/s, clock extraction in a 560 Mbit/s coaxial cable transmission system, and a modulo-n divider technique for timing generation using ECL feedback shift registers for frequencies up to 1.6 GHz. The demonstrations highlight the multiplexer´s ability to effectively extend the system speed limit of commercially available ECL from a few hundred Mbits/s to the Gbit/s range. An eight-input multiplexer using three chips in a hybrid assembly is demonstrated multiplexing a static input pattern up to 2.8 Gbits/s.