A 1500 gate, random logic, large-scale integrated (LSI) masterslice

Describes the development for the bipolar gate array masterslice for custom designed logic. One chip is designed containing an array of standard logic gates which are then interconnected in a custom manner by using the various levels of metal on the chip. One such masterslice contains 1500 logic gates. The authors describe the physical organization of the chip, and the software package used to assist in simulating the logic, wiring the chip, and generating the patterns needed to test that specific logic function. The internal gate is described in detail, and a discussion of some of the design tradeoffs made is included. The peripheral level-shifting circuits used to interface with a T/SUP 2/L environment and an on-chip reference generating circuit are described. The testing philosophy used, and the package within which the chip is placed are discussed. The paper concludes with a description of the bipolar process used to manufacture the chip.