• DocumentCode
    887755
  • Title

    Changing test and data modeling requirements for screening latent defects as statistical outliers

  • Author

    Turakhia, Ritesh P. ; Daasch, W. Robert ; Lurkins, Joel ; Benware, Brady

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA
  • Volume
    23
  • Issue
    2
  • fYear
    2006
  • Firstpage
    100
  • Lastpage
    109
  • Abstract
    The expanded role of test demands a significant change in mind-set of nearly every engineer involved in the screening of semiconductor products. The issues to consider range from DFT and ATE requirements, to the design and optimization of test patterns, to the physical and statistical relationships of different tests, and finally, to the economics of reducing test time and cost. The identification of outliers to isolate latent defects will likely increase the role of statistical testing in present and future technologies. An emerging opportunity is to use statistical analysis of parametric measurements at multiple test corners to improve the effectiveness and efficiency of testing and reliability defect stressing. In this article, we propose a "statistical testing" framework that combines testing, analysis, and optimization to identify latent-defect signatures. We discuss the required characteristics of statistical testing to isolate the embedded-outlier population; test conditions and test application support for the statistical-testing framework; and the data modeling for identifying the outliers.
  • Keywords
    integrated circuit reliability; integrated circuit testing; monolithic integrated circuits; statistical testing; data modeling requirements; latent defect signature screening; optimization; parametric measurement statistical analysis; reliability defect stressing; semiconductor product screening; statistical outliers; statistical testing framework; test modeling requirements; Application specific integrated circuits; Delay; Frequency; Large scale integration; Logic devices; Logic testing; Manufacturing; Microelectronics; Statistical analysis; Stress measurement; adaptive testing; data modeling; reliability; statistical outlier screening;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2006.37
  • Filename
    1613789