Title :
Test consideration for nanometer-scale CMOS circuits
Author :
Roy, Kaushik ; Mak, T.M. ; Cheng, Kwang-Ting
Author_Institution :
Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
The exponential increase in leakage, the device parameter variations, and the aggressive power management techniques will severely impact IC testing methods. Test technology faces new challenges as faults with increasingly complex behavior become predominant. Design approaches aimed at fixing some of the undesirable effects of nanometric technologies could jeopardize current test approaches. In this article, we explore test considerations for scaled CMOS circuits in the nanometer regime and describe possible solutions to many of these challenges, including statistical timing and delay test, IDDQ test under exponentially increasing leakage, and power or thermal management architectures.
Keywords :
CMOS integrated circuits; integrated circuit testing; leakage currents; nanoelectronics; statistical testing; IDDQ test; IC testing methods; device parameter variations; leakage current; nanometer-scale CMOS circuits; power management techniques; statistical delay test; statistical timing test; CMOS technology; Circuit faults; Circuit testing; Delay; Frequency; Silicon; Temperature dependence; Thermal management; Threshold voltage; Timing; deep-submicron test; delay test; nanometer technologies; statistical timing;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2006.52