DocumentCode
887831
Title
A practical method for reducing the effects of parasitic capacitances in integrated circuits
Author
Grebene, A.B.
Volume
55
Issue
2
fYear
1967
Firstpage
235
Lastpage
236
Abstract
In integrated circuits, effects of distributed junction capacitance associated with the diffused resistor structure can be reduced by isolating this capacitance from the ac ground. In this letter a pactical method of obtaining is such an isolation is proposed and analytical results are presented to verify iprovement in high frequency performance.
Keywords
Conductivity; Degradation; Electrons; Impurities; Parasitic capacitance; Photovoltaic cells; Photovoltaic systems; Protons; Silicon; Solar power generation;
fLanguage
English
Journal_Title
Proceedings of the IEEE
Publisher
ieee
ISSN
0018-9219
Type
jour
DOI
10.1109/PROC.1967.5458
Filename
1447388
Link To Document