Title :
Return Path Assumption Validation for Inductance Modeling in Digital Design
Author :
David, Lauréline ; Crégut, Corinne ; Huret, Fabrice ; Quéré, Yves ; Nyer, Frédéric
Author_Institution :
STMicroelectron., Crolles
fDate :
5/1/2007 12:00:00 AM
Abstract :
Inductance modeling for on-chip interconnects in a typical digital environment is proposed. Regarding the effective loop inductance computation, the issue of current return path assumptions is first discussed. Then, sensible assumptions about the return path localization are presented and systematically validated. Finally, representative structure models allowing prelayout effective inductance estimations are suggested.
Keywords :
digital integrated circuits; inductance; integrated circuit interconnections; integrated circuit modelling; digital design; inductance modeling; on-chip interconnects; return path assumption validation; return path localization; Circuit noise; Coupling circuits; Delay effects; Delay estimation; Frequency; Inductance; Integrated circuit interconnections; Propagation delay; RLC circuits; Working environment noise; Digital circuit; inductance; interconnection; modeling;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/TADVP.2007.896002
