DocumentCode :
888223
Title :
Optimizing the length of checking sequences
Author :
Hierons, Rob M. ; Ural, Hasan
Author_Institution :
Sch. of Inf. Syst., Comput. & Math., Brunel Univ., Uxbridge, UK
Volume :
55
Issue :
5
fYear :
2006
fDate :
5/1/2006 12:00:00 AM
Firstpage :
618
Lastpage :
629
Abstract :
A checking sequence, generated from a finite state machine, is a test sequence that is guaranteed to lead to a failure if the system under test is faulty and has no more states than the specification. The problem of generating a checking sequence for a finite state machine M is simplified if M has a distinguishing sequence: an input sequence D~ with the property that the output sequence produced by M in response to D is different for the different states of M. Previous work has shown that, where a distinguishing sequence is known, an efficient checking sequence can be produced from the elements of a set A of sequences that verify the distinguishing sequence used and the elements of a set γ of subsequences that test the individual transitions by following each transition t by the distinguishing sequence that verifies the final state of t. In this previous work, A is a predefined set and γ is defined in terms of A. The checking sequence is produced by connecting the elements of γ and A to form a single sequence, using a predefined acyclic set Ec of transitions. An optimization algorithm is used in order to produce the shortest such checking sequence that can be generated on the basis of the given A and Ec. However, this previous work did not state how the sets A and Ec should be chosen. This paper investigates the problem of finding appropriate A and Ec to be used in checking sequence generation. We show how a set A may be chosen so that it minimizes the sum of the lengths of the sequences to be combined. Further, we show that the optimization step, in the checking sequence generation algorithm, may be adapted so that it generates the optimal Ec. Experiments are used to evaluate the proposed method.
Keywords :
finite state machines; formal specification; formal verification; minimisation; checking sequence generation algorithm; finite state machine; optimization algorithm; test minimisation; test sequence; Automata; Character generation; Circuit testing; Communication system control; Computer Society; Joining processes; Minimization; Protocols; Specification languages; System testing; Finite state machine; checking sequence; distinguishing sequence.; test minimization;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2006.80
Filename :
1613841
Link To Document :
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