Bipolar structures for BIMOS technologies

Recent advances in LSI and VLSI have offered many possibilities in mixing MOSFET and bipolar integrated structures on the same chip. The authors study the integration of bi-polar structures in BIMOS environments. More specifically bipolar structures are studied under the constraints and guidelines of a given MOS technology, e.g., the nonexistence of an n/SUP +/ underlayer, and the high epitaxial (substrate) resistivity. A bipolar structure, based on merging a multicollector p-n-p transistor with a multiemitter n-p-n transistor is proposed. The structure takes advantage of the availability of clock signals on a MOS chip, and uses the epitaxial (substrate) resistance as a load. It can be used to realize logic and memory functions. Computer simulation as well as experimental results show that the structure can perform efficiently in both BIMOS and bipolar technologies.