Title :
A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS ICs
Author :
Koh, Jeongwook ; Schmitt-Landsiedel, Doris ; Thewes, Roland ; Brederlow, Ralf
Author_Institution :
Tech. Univ. Munich
fDate :
6/1/2007 12:00:00 AM
Abstract :
We present a novel principle for 1/f noise reduction in linear analog CMOS ICs. The principle is experimentally demonstrated for a two-stage CMOS Miller operational amplifier in a standard 0.12-mum, 1.5-V digital CMOS technology. A threefold 1/f noise reduction (5 dB) is achieved at 10 Hz compared with a reference circuit. The impact of the principle on the circuit performance is investigated
Keywords :
1/f noise; CMOS analogue integrated circuits; MOS integrated circuits; integrated circuit noise; linear network synthesis; operational amplifiers; 0.12 micron; 1.5 V; 1/f noise reduction; 10 Hz; CMOS Miller operational amplifier; complementary switched MOSFET; digital CMOS technology; linear analog CMOS IC; switched bias technique; CMOS process; CMOS technology; Circuit noise; Low-frequency noise; MOSFET circuits; Noise cancellation; Noise reduction; Radio frequency; Sampling methods; Signal to noise ratio; 1/f noise reduction; CMOS linear analog IC; switched bias technique;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.897144
