DocumentCode :
888794
Title :
A Receiver Architecture for Dual-Antenna Systems
Author :
Rafati, Hamid ; Razavi, Behzad
Author_Institution :
Univ. of California, Los Angeles
Volume :
42
Issue :
6
fYear :
2007
fDate :
6/1/2007 12:00:00 AM
Firstpage :
1291
Lastpage :
1299
Abstract :
The signals received by two antennas can be processed by a single time-shared receiver but only in the absence of interferers and channel-select filters. A low-IF receiver architecture is introduced that translates two antenna signals to positive and negative frequencies in the complex domain, reducing the number of baseband A/D converters by a factor of two. A dual-receiver prototype designed and fabricated in 0.18-mum CMOS technology provides a sensitivity of -72 dBm with an EVM of -25 dB for 64 QAM signals while drawing 60.2 mW from a 1.8-V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; multifrequency antennas; radio receivers; signal processing; CMOS technology; antenna signals; baseband A/D converters; channel-select filters; dual receiver; dual-antenna systems; low-IF receiver; signal processing; single time-shared receiver; size 0.18 mum; voltage 1.8 V; Baseband; CMOS technology; Filtering; Filters; MIMO; OFDM; Quadrature amplitude modulation; Receiving antennas; Signal design; Signal processing; CMOS receivers; IEEE 802.11a; MIMO; low-IF; orthogonal frequency division multiplexing (OFDM); wireless local area network (WLAN);
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2007.897150
Filename :
4214982
Link To Document :
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