A synchronous switched capacitor filter [CMOS Si-gate implementation]

A new switched capacitor circuit is presented, realizing a moderate to high Q frequency emphasizing network. The original feature of this circuit is that its resonant frequency is equal to one half of the sampling frequency, and independent of the accuracy of the capacitor ratio or of any imperfection, both affecting only the Q factor. The gain is nearly proportional to the Q factor. An experimental circuit has been implemented in CMOS Si-gate technology with a programmable gain of 20 dB and 40 dB, corresponding to a Q factor of 8.6 and 79, respectively. Experimental results are in good agreement with the theory. Modifications of the basic circuit are proposed to cancel the effects of parasitic capacitances and to reduce the chip area.