CRRES microelectronic test chip orbital data. II

Author

Soli, G.A. ; Blaes, B.R. ; Buehler, M.G. ; Ray, K. ; Lin, Y-S

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

Volume

39

Issue

6

fYear

1992

fDate

12/1/1992 12:00:00 AM

Firstpage

1840

Lastpage

1845

Abstract

Data from a MOSFET matrix on two JPL (CIT Jet Propulsion Laboratory) CRRES (Combined Release and Radiation Effects Satellite) chips, each behind different amounts of shielding, are presented. Space damage factors are nearly identical to ground test values for pMOSFETs. The results from neighboring rows of MOSFETs show similar radiation degradation. The SRD (Space Radiation Dosimeter) is used to measure the total dose accumulated by the JPL chips. A parameter extraction algorithm that does not underestimate threshold voltage shifts is used. Temperature effects are removed from the MOSFET data

Keywords

MOS integrated circuits; aerospace instrumentation; insulated gate field effect transistors; integrated circuit testing; radiation effects; radiation hardening (electronics); semiconductor device testing; CMOS; Combined Release and Radiation Effects Satellite; JPL CRRES chips; MOSFET matrix; Space Radiation Dosimeter; flight dosimeters; microelectronic test chip orbital data; parameter extraction algorithm; radiation degradation; space damage factors; total dose; Degradation; Extraterrestrial measurements; Laboratories; MOSFET circuits; Microelectronics; Propulsion; Radiation effects; Satellites; Semiconductor device measurement; Testing;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.211375

Filename

211375