Qualifying commercial ICs for space total-dose environments

A test protocol based on MIL-STD-883D, Test Method 1019.4, which includes a room-temperature biased anneal following irradiation, is shown to predict device response to low-dose-rate irradiations more accurately than the present standard. Failure dose was measured with three test protocols: with Method 1019.4, with Method 1019.4 plus a room-temperature anneal, and with 0.2 rad(Si)/s irradiations at static and dynamic bias. In comparing the power-supply current (I_DD) of two commercial field-programmable gate arrays (FPGAs), it was found that the failure dose for devices with a high annealing rate increased by a factor of ten times when a room-temperature anneal was included, while devices with a slower annealing rate showed almost a two-times improvement in failure dose. Slower-annealing devices showed a higher failure dose when dynamically biased during low dose-rate irradiations, indicating that radiation-induced charge neutralization accelerated recovery in these devices. Methods of characterizing the hardness of MOS ICs using a test flow that includes room-temperature and elevated-temperature anneals are discussed