• DocumentCode
    888947
  • Title

    The Maximum Rate Accumulator

  • Author

    Loomis, H.H., Jr.

  • Author_Institution
    Department of Electrical Engineering, University of California, Davis, Calif.
  • Issue
    4
  • fYear
    1966
  • Firstpage
    628
  • Lastpage
    639
  • Abstract
    This paper concerns the application of a result of Arden and Arthurs to a particular finite-state machine, the accumulator. Arden and Arthurs have shown that given a complete set of devices for some fixed sequence rate, any finite-state machine may be constructed from these devices to operate at this maximum rate. In this paper we consider the construction of a good representation (in terms of overall delay) of the m-bit accumulator, operating at the maximum rate. Examples are presented using state-of-the-art devices which illustrate the construction and give measures of usefulness and cost Of this accumulator.
  • Keywords
    Algebra; Calculus; Computer networks; Delay; Logic circuits; Logic design; Logic devices; Network synthesis; Pattern classification; Switching circuits;
  • fLanguage
    English
  • Journal_Title
    Electronic Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0367-7508
  • Type

    jour

  • DOI
    10.1109/PGEC.1966.264386
  • Filename
    4038837