DocumentCode
889106
Title
Subnanosecond Self-Aligned I/sup 2/L/MTL Circuits
Author
Tang, D.D. ; Ning, Tak H. ; Isaac, Randall D. ; Feth, George C. ; Wiedmann, Siegfried K. ; Yu, Hwa-Nien
Volume
15
Issue
4
fYear
1980
Firstpage
444
Lastpage
449
Abstract
A self-aligned I/sup 2/L/MTL technology featuring collectors doped from and contacted by polysilicon, self-aIigned collector and base contact edges, and metal-interconnected bases is described. Experimental ring-oscillator circuits designed with 2.5-/spl mu/m design roles and fabricated with this technology exhibit gate delays as small as 0.8 ns at lC = 100 -/spl mu/A for fan-in = 1 and fan-out = 3. Increased wiring flexibility and improved circuit density are inherent advantages of this self-aligned technology.
Keywords
Bipolar integrated circuits; Integrated circuit technology; Integrated logic circuits; Delay; Electron devices; Fabrication; Integrated circuit technology; Large scale integration; Lithography; Logic devices; Silicon; Wiring;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1980.1051419
Filename
1051419
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