On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement

The authors propose a unified approach to the design of the fault-tolerant systolic arrays incorporating design for testability, a testing scheme, a reconfiguration algorithm, time-complexity analysis of the proposed reconfiguration algorithm, and yield analysis. A main feature of the proposed designs is that multiple processing elements in a 2-D array can be tested simultaneously, thus reducing the testing time significantly. Another feature is that with the introduction of delay registers, the proposed reconfiguration algorithm reconfigures a faulty 2-D systolic array into a fault-free array without reducing throughput. The overall aim is to provide a design for a 2-D systolic array that produces high yield in VLSI/WSI implementations