On implementing large binary tree architectures in VLSI and WSI

The authors present an efficient scheme for the layout of large binary-tree architectures by embedding the complete binary tree in a two-dimensional array of processing elements. Their scheme utilizes virtually 100% of the processing elements in the array as computing elements; it also shows substantial improvements in propagation delay and maximum edge length over H-tree layouts. They shown that their layouts readily lend themselves to fault-tolerant designs for overcoming fabrication defects in large-area and wafer-scale implementations of binary-tree architectures