A 4-Mbit Full-Wafer ROM

A 4-Mbit full-wafer MOS ROM on a 3-in silicon wafer has been designed and characterized. A novel cell structure is utilized in the memory, which results in a small cell area, 99 /spl mu/m/sup 2/, with 5-/spl mu/m design roles. Efficient defect-tolerant technologies including memory-cell duplication and fail-safe operation are incorporated in order to prevent a decrease in fabrication yield which inevitably occurs in wafer-scale integration. The ROM is composed of four 1-Mbit modules. 3760 characters represented by 18 X 16 dot matrices, most of which are Chinese ideographs (KANJI), are stored in each module as mask ROM data, Memory organization is suitably designed for JIS (Japanese Industrial Standard) KANJI Code and the matrix size. A character is accessed in 12 /spl mu/s, and 16-bit-wide data are transferred by an internal counter synchronized with an external 1-MHz clock. Measured on-chip power dissipation is 2 W for a full wafer.