• DocumentCode
    889928
  • Title

    Test algorithms for double-buffered random access and pointer-addressed memories

  • Author

    Van Sas, Jos ; Catthoor, Francky ; De Man, Hugo J.

  • Volume
    10
  • Issue
    2
  • fYear
    1993
  • fDate
    6/1/1993 12:00:00 AM
  • Firstpage
    34
  • Lastpage
    44
  • Abstract
    Test algorithms for static double-buffered RAMs and pointer-addressed memories (PAMs) are presented. The reasons why test algorithms for single-buffered memories are inadequate to test double-buffered memories (DBMs) are discussed. To obtain a realistic fault model, the authors perform an inductive fault analysis on the DBM cells. They also show that the address generation method imposes different requirements on the test algorithms.<>
  • Keywords
    SRAM chips; integrated circuit testing; integrated memory circuits; DBM cells; PAMs; address generation method; double-buffered memories; double-buffered random access; fault model; inductive fault analysis; pointer-addressed memories; static double-buffered RAMs; test algorithms; Application software; Decoding; Digital signal processing; Digital signal processing chips; Master-slave; Read-write memory; Signal processing algorithms; Signal synthesis; Telecommunication computing; Testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.211526
  • Filename
    211526
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=889928