10 Gbit/s clock recovery circuit using temperature compensated dielectric resonator filter

A clock recovery circuit using a dielectric resonator filter (DRF) for 10 Gbit/s data regeneration is presented. Where a temperature compensation technique was for the first time employed to keep the relative phase between the input data and clock to the decision circuit as constant as possible. The experimental results showed an output clock phase variation of <±6 deg over the operating temperature range from 0-75°C and the measured maximum RMS jitters of <2 ps with the resonance detunings of up to ±10 MHz