DocumentCode
890512
Title
Synthesis of UP-DOWN Counters
Author
Kain, Richard Y.
Author_Institution
Dept. Elec. Engrg., University of Minnesota, Minneapolis, Minn. 55455.
Issue
2
fYear
1967
fDate
4/1/1967 12:00:00 AM
Firstpage
146
Lastpage
151
Abstract
IN this paper we will describe an algorithm for the decomposition of UP-DOWN counters. The constituents of the decomposed counters will be UP-DOWN counters of small modulus and small amounts of combinatorial logic. The main advantage accruing from this decomposition technique is that only a small number of building blocks is required to build counters with any modulus. We will begin the discussion by developing analysis techniques for particular interconnections of UP-DOWN counters. Following this, a general technique for the synthesis of an UP-DOWN counter with any modulus will be given. Only binary and ternary UP-DOWN counters and a small amount of combinatorial logic will be required.
Keywords
Clocks; Correlation; Counting circuits; Hardware; Logic design; Magnetic heads; Optimization methods; Signal synthesis; Size measurement; Synchronization; Counters; logic design; switching theory;
fLanguage
English
Journal_Title
Electronic Computers, IEEE Transactions on
Publisher
ieee
ISSN
0367-7508
Type
jour
DOI
10.1109/PGEC.1967.264809
Filename
4039021
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