DocumentCode
890540
Title
A highly sensitive strobed comparator
Author
Yukawa, Akira
Volume
16
Issue
2
fYear
1981
fDate
4/1/1981 12:00:00 AM
Firstpage
109
Lastpage
113
Abstract
A sensitive strobed comparator has been designed and extensively characterized. It is realized in a standard NMOS silicon-gate process, occupying a die area of 0.05 mm/SUP 2/ (81/mil/SUP 2/). Power consumption is 1 mW from a single 10 V supply. Resolution is 0.5 mV when a strobe signal rise from 0 V to 5 V in 20 ns. Offset voltage had a mean value of -0.5 mV with a standard deviation of 5 mV. This comparator should be useful for high-resolution analog-digital converters in NMOS technology.
Keywords
Analogue-digital conversion; Comparators (circuits); Field effect integrated circuits; analogue-digital conversion; comparators (circuits); field effect integrated circuits; Analog-digital conversion; Circuit noise; Coupling circuits; Differential amplifiers; Feedback; Flip-flops; Large scale integration; Noise generators; Pulse amplifiers; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1981.1051552
Filename
1051552
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