Charge redistribution codec

A charge redistribution codec fabricated by NMOS technology is presented which uses only one capacitor array, thereby resulting in improved accuracy, speed, and chip area utilization. The realization of this scheme requires precision voltage references which are described. A description of a codec complete with logic to interface a full duplex PCM link is included. The chip has provision for asynchronous transmit/receive, direct and microcomputer control and internal power down. The introduction of an improved method for offset correction eliminates the need for off-chip autozero circuitry.