DocumentCode :
890661
Title :
Array Networks for a Parallel Adder and Its Control
Author :
Aleksander, I.
Author_Institution :
Dept. Elec. Engrg., Queen Mary College, University of London, London E.1., England.
Issue :
2
fYear :
1967
fDate :
4/1/1967 12:00:00 AM
Firstpage :
226
Lastpage :
229
Abstract :
A collection of array-like networks of two-input AND gates is described with particular reference to their use in a parallel adder. These networks have properties which facilitate their incorporation in high-capability monolithic circuits. This leads to the adoption of a radix R and a one-in-R binary code. A decimal system is discussed and compared with a pure binary one. The application of the array networks to other digital tasks is illustrated by the design of routing circuits which enable the adder to subtract, multiply, and divide.
Keywords :
Adders; Circuits; Computer networks; Costs; DH-HEMTs; Error correction; Inspection; Linear approximation; Logic; Piecewise linear techniques; Adder; arithmetic operations; array networks; carry processing; decimal addition; digit routing; monolithic circuits; numerical processor; parallel addition;
fLanguage :
English
Journal_Title :
Electronic Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0367-7508
Type :
jour
DOI :
10.1109/PGEC.1967.264581
Filename :
4039037
Link To Document :
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