Title :
A 16-bit self-testing multiplier
Author :
Rainard, Jean-Luc ; Vernay, Yves-Jacques
fDate :
6/1/1981 12:00:00 AM
Abstract :
A self-testing circuit is presented, i.e., a circuit able to signal out any inner fault. It is a 16-bit serial-parallel multiplier, based on a 2-bit Booth algorithm; data are coded in two´s complement. The use of a rather cheap self-testing technique based on parity predicting results in the realization of a `self-testing-only´ circuit requiring only about 25 percent extra silicon area. This realization permitted to study the feasibility of self-testing circuits. Critical points are also pointed out, such as the testing of I/O pins.
Keywords :
Fault tolerant computing; Integrated circuit testing; Logic testing; Multiplying circuits; fault tolerant computing; integrated circuit testing; logic testing; multiplying circuits; Built-in self-test; Circuit faults; Data processing; Electrical fault detection; Fault detection; Integrated circuit reliability; Microprocessors; Performance evaluation; Pollution; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1981.1051569
