Title :
A 3-ns 1-kbit RAM using super self-aligned process technology
Author :
Sakai, Tetsushi ; Yamamoto, Yousuke ; Kobayashi, Yoshiji ; Kawarada, Kuniyasu ; Inabe, Yasunobu ; Hayashi, Toshio ; Miyanaga, Hiroshi
Abstract :
A high speed 1-kbit ECL RAM with a typical access time of 2.7 ns and power dissipation of 500 mW has been developed, using a novel LSI fabrication process technology, together with a new reference circuit configuration. This paper describes an integrated transistor structure using this novel process technology, fabrication steps, a new sense circuit and performance of the RAM.
Keywords :
Bipolar integrated circuits; Emitter-coupled logic; Integrated memory circuits; Large scale integration; Random-access storage; bipolar integrated circuits; emitter-coupled logic; integrated memory circuits; large scale integration; random-access storage; Boron; Digital systems; Electrodes; Etching; Fabrication; Integrated circuit technology; Large scale integration; Paper technology; Power dissipation; Read-write memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1981.1051617
