Title :
A 4Kx8 dynamic RAM with self-refresh
Author :
Reese, Edmund A. ; Spaderna, Dieter W. ; Flannagan, Stephen T. ; Tsang, Fred
Abstract :
A 4K/spl times/8 MOS dynamic RAM using a single transistor cell with on-chip self-refresh is described. The device uses a multiplexed address/data bus. Control of the reconfigurable data bus allows the RAM to operate on either an 8-bit or a 16-bit data bus. The memory cell is fabricated using a double polysilicon n-channel HMOS technology using polysilicon word lines and metal bit lines. Self-refresh is implemented with an on-chip timer, arbiter, counter and multiplexer. A high-speed arbiter resolves simultaneous memory and refresh requests. Redundant rows are used for increased manufacturing yields. Polysilicon fuses are electrically programmed to select redundant rows.
Keywords :
Field effect integrated circuits; Integrated memory circuits; Large scale integration; Random-access storage; field effect integrated circuits; integrated memory circuits; large scale integration; random-access storage; Clocks; DRAM chips; Microprocessors; Packaging; Pins; Random access memory; Read-write memory; Resistors; Timing; Variable structure systems;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1981.1051626
