A 34 /spl mu/m/SUP 2/ DRAM cell fabricated with a 1 /spl mu/m single-level polycide FET technology

Dynamic RAM test arrays have been fabricated using a single-level polycide FET technology and a cell layout in which the top electrode of a given cell storage capacitor is provided by the adjacent word line. This layout achieves the same density as the conventional double-polysilicon cell, and comparable performance is obtained using a low-resistance polycide word line. Hi-C implants in the storage region provide increased capacitance, better isolation, and reduced transient noise. Design and operation considerations for the cell and arrays are described and measured results are compared to the design values. A cell area of 34 /spl mu/m/SUP 2/ is achieved using a scaled-down n-channel FET technology with a 22.5 nm gate oxide and 1 /spl mu/m minimum mask feature size.