DocumentCode
891292
Title
A bipolar 2500-gate subnanosecond masterslice LSI
Author
Nakaya, Masao ; Kato, Shuichi ; Tsukamoto, Katsuhiro ; Sakurai, Hiromi ; Kondo, Takashi ; Horiba, Yasutaka
Volume
16
Issue
5
fYear
1981
Firstpage
558
Lastpage
562
Abstract
A bipolar 2500-gate subnanosecond masterslice LSI has been developed for use in computer mainframes. A walled-emitter structure has been realized by using double boron ion implantation with an n-type epitaxial layer to obtain high performance and high packing density. A new cell composed of a pair of adjacent gates provides high utilization of input transistors. A gate delay of 0.58 ns with power dissipation of 0.54 mW/gate has been achieved. The masterslice has been applied to an 18-bit memory data register circuit consisting of 1983 internal logic gates and has been mounted on a new 224-pin plug-in package.
Keywords
Bipolar integrated circuits; Cellular arrays; Integrated logic circuits; Large scale integration; bipolar integrated circuits; cellular arrays; integrated logic circuits; large scale integration; Boron; Delay; Epitaxial layers; Ion implantation; Large scale integration; Logic circuits; Logic gates; Packaging; Power dissipation; Registers;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1981.1051637
Filename
1051637
Link To Document