Design Considerations for a Parallel Bit-Organized MOS Memory

This paper discusses the design trade-offs for a parallel bit-organized MOS memory. A memory capacity of 40K bits can be achieved using LSI techniques. Memory storage capacity is expandable in both word length and number of words stored. The physical dimensions of the memory should be considerably smaller than those of a comparable core design. Power consumption per bit should likewise be less than that achievable with cores. A full cycle time of 1 us or less can be achieved. Cost per bit should compare very favorably with that of a core design.