Diagnosis of Large Combinational Networks

A method is described for constructing a set of input patterns able to detect every given failure of a combinational network. The result may not be a minimal set of tests, but it is surely a complete test. The procedure is designed for large networks with high number of independent inputs. It can deal with networks including any elementary logical gates such as AND, OR, NAND, NOR, and NOT. No limitations on fan-out are considered. The method can treat any class of single or multiple logical failures which can be described by means of a transformation of the logic equations of the network. The conventional description of the failures as one wire stuck at one or stuck at zero is not required. This can be useful in detection of wiring errors in equipment testing. The basis of the procedure is a ``choice technique´´ which avoids, in most cases, the two-level expansion of the mapping realized by the network. The procedure is illustrated in detail and two application examples to the detection of a single wire stuck at zero failure and of a wiring error are given.