High-speed low-power silicon MESFET parallel multipliers

Author

Hartgring, Cornelis D. ; Rosario, Binoy A. ; Pickett, James M.

Volume

17

Issue

1

fYear

1982

fDate

2/1/1982 12:00:00 AM

Firstpage

69

Lastpage

73

Abstract

The design of fast low-power silicon LSI MESFET parallel multipliers is studied. The architecture of the multipliers and the designs of the functional blocks are discussed. The overall performance of the multipliers is estimated from the simulated performances of the functional blocks and from system simulations with a logic simulator. The actual performance of 8×8 and 10×10 bit TTL-compatible multipliers, fabricated with a 2.5 μm silicon MESFET technology (1.5-2 μm effective dimensions) is compared to the simulations.

Keywords

Digital arithmetic; Digital integrated circuits; Elemental semiconductors; Field effect integrated circuits; Large scale integration; Schottky gate field effect transistors; Signal processing; Silicon; digital arithmetic; digital integrated circuits; elemental semiconductors; field effect integrated circuits; large scale integration; signal processing; silicon; Adders; Circuit simulation; Digital signal processing; Laboratories; Large scale integration; Logic; MESFET circuits; Performance evaluation; Propagation delay; Silicon;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1982.1051688

Filename

1051688