DocumentCode
891853
Title
A new method for realizing JFETs and super B´s in a standard bipolar IC process
Author
Nordholt, Ernst H. ; Nauta, P.K. ; van der Veen, M.
Volume
17
Issue
1
fYear
1982
Firstpage
81
Lastpage
83
Abstract
A new method for the realization of p-channel JFETs is presented. It is based on the removal of thin silicon layers by repeated anodic oxidation and etching, allowing the shallow-n (SN) diffusion to penetrate deeper into the shallow-p (SP) region. JFETs with a thin channel are thus obtained with a high yield and good reproducibility.
Keywords
Integrated circuit technology; Junction gate field effect transistors; Monolithic integrated circuits; Semiconductor technology; integrated circuit technology; junction gate field effect transistors; monolithic integrated circuits; semiconductor technology; Bipolar integrated circuits; Bipolar transistors; Breakdown voltage; Fabrication; JFETs; Reproducibility of results; Silicon; Solid state circuits; Switching circuits; Tin;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1982.1051691
Filename
1051691
Link To Document