MOS Device and Technology Constraints in VLSI

As devices and technology are scaled to achieve performance and density improvements, a number of constraints come into play. These constraints apply to both the parasitic as well as the intrinsic device and reduce the benefits that would have otherwise been available from scaling. In this paper, a number of performance limiters are pointed out. Specifically, velocity saturation, parasitic sourced-drain series resistance, finite channel thickness, and hot-carrier effects are analyzed and their effects on performance are evaluated. Future trends as impacted by these limiters are explored for both p- and n-charnel devices.