• DocumentCode
    892102
  • Title

    Verifying command sequences for satellite systems

  • Author

    Peters, James F., III ; Ramanna, Sheela

  • Author_Institution
    Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
  • Volume
    7
  • Issue
    10
  • fYear
    1992
  • Firstpage
    14
  • Lastpage
    21
  • Abstract
    A formal basis for the design of a checker used in validating safe schedules and in selecting error recovery schedules for satellite control systems is presented. This design includes a high-level specification of checker behavior and properties (called flight rules) of safe schedules. Specifications are written in timed linear logic (TLL). Validation of schedules is performed in terms of real-time telemetry and deduction system proof rules. Telemetry (state information for satellite subsystems) serves as input to the checker. Detection of violation of a flight rule by the checker results in the selection of a contingency plan (error recovery schedule). The checker is illustrated by an example involving the TOPEX/Poseidon Oceanographic Satellite System.<>
  • Keywords
    aerospace computer control; artificial satellites; fault tolerant computing; formal specification; system recovery; telemetering systems; TOPEX/Poseidon Oceanographic Satellite System; command sequences verification; contingency plan; design; error recovery schedules; flight rules; real-time telemetry; safe schedules; satellite control; timed linear logic; Computer errors; Control systems; Laboratories; Logic; Processor scheduling; Propulsion; Satellites; Space vehicles; Telemetry; Timing;
  • fLanguage
    English
  • Journal_Title
    Aerospace and Electronic Systems Magazine, IEEE
  • Publisher
    ieee
  • ISSN
    0885-8985
  • Type

    jour

  • DOI
    10.1109/62.161488
  • Filename
    161488