A Fine-Line nMOS IC for Raster-Scan Control of a 500-MHz Electron-Beam Deflection System

A 700-transistor fine-line nMOS chip was developed for the deflection control in a 500-MHz electron-beam deflection system. This circuit produces a differential output carrier staircase into a 25-Omega load with a programmable offset from a 5-bit D/A converter. Synchronized to the staircase is a 4-V beam-blanking pulse of programmable width which also drives a 25-/spl Omega/ load. Extensive use of feed-forward circuit techniques is employed to insure the staircase and beam-blanking outputs have rise and fall times less than 500 ps. A two-phase clock generated on chip from the master clock input is used to drive two 16-stage dynamic shift registers. All of the clock and data inputs are ECL compatible. The average gate delays through two major sections of the chip are 200 ps and 250 ps at a chip power dissipation of 1.2 W. Circuit operation up to 790 MHz without cooling and 1000 MHz with freon cooling has been obtained. This circuit utilizes 0.5-/spl mu/m effective channel length nMOS transistors fabricated with X-ray lithography and is an example of the performance achievable with this technology.