Multidrain NMOS for VLSI Logic Design

A multidrain NMOS circuit configuration (MD) is studied and its advantages over the conventional pull-up pull-down (PUD) configuration are discussed. These include efficient use of silicon area, less sensitivity to interconnections, less delay times, a controlled value of logic swing which is independent of VDD, and the possibility of integrating into a stacked structure where the load does not consume silicon real state. The MD and the PUD configurations are compatible and the latter is used where a large fan-out is required.