Complex integrated circuit design strategy

Presents a design strategy for VLSI circuits based on the use of a floor plan as an evaluation and management guide for the design of a future circuit. This approach is widely used in the microelectronic industry and allows global optimizations, which are the key to both high density and design reliability, by improving the assembly and the direct wiring of the blocks. The efficiency of such an approach may be improved by the use of a topological evaluator. This tool will give an evaluation of the shape, size, and connections of the main blocks from their specifications. It is able to take into account the topological constraints given by the designer in order to improve the assembly and connectivity of the floor plan. This tool is composed of a set of evaluation routines for the different kinds of functional blocks constituting a VLSI circuit and a supervisor for dialogue with the user.