A redundancy circuit for a fault-tolerant 256K MOS RAM

A multiple word/bit line redundancy technique introduced into a fault-tolerant 256K MOS RAM is described. The address of the defective lines are stored in spare decoders and defective lines are replaced by redundant lines. New electrically programmable elements are used in these spare decoders. Yield improvement as a result of the implementation of the redundant lines is discussed, and a detailed description of the redundancy circuit design is given. The redundancy occupies less than 10 percent of the whole chip area of the 256K MOS RAM. The good (defect-free) chip functions without any degradation of speed and power caused by the redundancy, while the power consumption and access time increases in the repaired chip are 10 and 25 percent, respectively.