DocumentCode
893138
Title
HMOS III technology
Author
Langston, Jerrod ; Hazani, E. ; Sachdev, S. ; Fuchs, Kerstin
Volume
17
Issue
5
fYear
1982
fDate
10/1/1982 12:00:00 AM
Firstpage
810
Lastpage
815
Abstract
A third-generation single-poly high-performance NMOS technology has been developed. The technology features scaled MOS devices with 250 Å gate and 0.25 pJ speed-power product. The technology integrates advanced processing capabilities in lithography and dry etching to achieve a depletion-load static memory cell size of 0.98 mils/SUP 2/. A 4K static RAM test vehicle has been fabricated with sub-15 ns access time. The technology has a major application in the shrink of existing microcomputers designed on previous HMOS technologies.
Keywords
Field effect integrated circuits; field effect integrated circuits; Boron; Capacitance; Doping; Implants; MOS devices; Microcomputers; Read-write memory; Ring oscillators; Testing; Vehicles;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1982.1051823
Filename
1051823
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