Title :
HMOS III technology
Author :
Langston, Jerrod ; Hazani, E. ; Sachdev, S. ; Fuchs, Kerstin
fDate :
10/1/1982 12:00:00 AM
Abstract :
A third-generation single-poly high-performance NMOS technology has been developed. The technology features scaled MOS devices with 250 Å gate and 0.25 pJ speed-power product. The technology integrates advanced processing capabilities in lithography and dry etching to achieve a depletion-load static memory cell size of 0.98 mils/SUP 2/. A 4K static RAM test vehicle has been fabricated with sub-15 ns access time. The technology has a major application in the shrink of existing microcomputers designed on previous HMOS technologies.
Keywords :
Field effect integrated circuits; field effect integrated circuits; Boron; Capacitance; Doping; Implants; MOS devices; Microcomputers; Read-write memory; Ring oscillators; Testing; Vehicles;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1982.1051823
