Title :
A storage-node-boosted RAM with word-line delay compensation
Author :
Fujishima, Kazuyasu ; Shimotori, Kazuhiro ; Ozaki, Hideyuki ; Nakano, Takao
Abstract :
A storage-node-boosted (SNB) RAM has been proposed and its advantages have been made clear for the VLSI memory. The new dynamic RAM architecture features the pulsed cell plates rather than the fixed potential cell plates, which stores 1.7 V/SUB DD/ for `H´ in the cell without any boosted clocks and compensates the word-line delay. The 1 kbit test array has been fabricated with a 2 /spl mu/m level design rule. It provides a signal charge level of over 300 fC and a speed-up of 20 ns in a reading operation compared with the fixed cell plate potential cell.
Keywords :
Field effect integrated circuits; field effect integrated circuits; Capacitance; Clocks; DRAM chips; Delay; Random access memory; Read-write memory; Signal detection; Testing; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1982.1051833
