Design parameters of the Hi-C DRAM cell

The Hi-C DRAM cell is a 1T cell where the storage capacitance is enhanced by using two cell implants to increase the depletion capacitance contribution. Moreover, a valuable feature of the cell is the capability of grounding the storage plate. This, however, causes the creation of a depletion layer at the surface which results in an effective capacitance that is smaller than the oxide capacitance. To minimise the capacitance reduction, the cell implant doses have to increase, which in turn lowers the breakdown voltage in the storage area. In this paper, the choice of the grounded-plate Hi-C cell process parameters, as constrained by breakdown, to provide advantageous charge capacity is investigated. The outcome is a chart defining a design window for the cell parameters which displays in a simple way the various tradeoffs.