Title :
An LSI adaptive array processor
Author :
Kondo, Toshio ; Nakashima, Takayoshi ; Aoki, Makoto ; Sudo, Tsuneta
fDate :
4/1/1983 12:00:00 AM
Abstract :
Describes an LSI adaptive array processor (AAP) for two-dimensional data processings. The AAP contains a large number of one-bit processing elements (PEs) arranged in a square array. The large degree of parallelism and control registers in each PE allow for high speed and flexible operations. High transfer capability is also obtained by a simple inter-PE connection network with hierarchical bypasses. The high applicability to various data processings is indicated by a matrix multiplication example, utilizing an algorithm similar to a systolic one. An AAP LSI composed of 8/spl times/8 PEs with powerful functions has been implemented in a 96.0 mm/SUP 2/ chip by using 2 /spl mu/m Si-gate p-well CMOS technology. A high-speed cycle time of 55 ns, low power dissipation of 1.1 W, and high packing density of 1170 transistors/mm/SUP 2/ has been achieved by a skilful manual design. Though the LSI contains as many as 111900 transistors, the design effort has only required one man-year due to cellular array regularity. This LSI is expected to realize a high-performance AAP compactly.
Keywords :
Cellular arrays; Computer architecture; Field effect integrated circuits; Large scale integration; Microprocessor chips; Parallel processing; cellular arrays; computer architecture; field effect integrated circuits; large scale integration; microprocessor chips; parallel processing; Adaptive arrays; Adaptive control; CMOS technology; Data processing; Hardware; Integrated circuit interconnections; Large scale integration; Power dissipation; Registers; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1983.1051915