A high speed GaAs 8-bit multiplexer using capacitor-coupled logic

Capacitor-coupled logic has been used to design and fabricate a GaAs eight channel multiplexer IC for use at 1.2 Gbit/s, which is fully compatible with ECL, and which offers good stability and very high tolerances to device parameters and circuit voltages. A technique has been developed to enable initial charging of all the coupling capacitors, upon application of a simple pulse sequence to control lines. Preliminary results show correct operation of the multiplexer when operated on wafer probes up to 250 MHz, the present practical limit for such measurements. Higher frequency measurements will be carried out on packaged devices, but these results are not yet available. The divide-by-two elements in the multiplexer can be programmed to self oscillate at /SUP 1///SUB 4/ their maximum usable frequency, allowing simple testing of high frequency performance. A very good agreement between the measured maximum usable frequencies and those predicted from the oscillation frequencies has been achieved, with over 60 percent yield for dividers. On the basis of these preliminary results, indicating operation at speeds up to about 600 MHz, it is anticipated that future wafers with 1 /spl mu/m gate lengths will operate at 1.2 Gbits/s.