A 20K-gate CMOS gate array

Combining an advanced 2-/spl mu/m CMOS technology with a newly developed triple-level metallization technology, a high-performance 20K-gate CMOS gate array has been developed. The advantage of triple-level metallization for area saving in a large-scale gate array was evaluated by a computer simulation. The typical gate delay is 1.5 ns with fan-out of 3, and 3-mm metal interconnect length. As a test vehicle for verifying the high-performance gate array, a 32/spl times/32-bit parallel multiplier has been successfully designed and fabricated. Cell utilization is about 65%. A typical multiplication takes 120 ns at a 5-MHz clock rate, with a power dissipation of 400 mW.