Junction charge-coupled logic (JCCL)

Junction charge-coupled devices (JCCDs) offer advantages over conventional charge-coupled devices in the area of logic applications. These advantages are based on the fact that charge can be injected and detected through the steering gates of the JCCD, thus offering the possibility of three-dimensional charge transport. These unique charge injection and detection structures have been used to design basic logic functions, such as AND, OR, INVERT, and REGENERATE. A very simple bipolar process, using only five masking steps and 7.5-μm layout rules has been used to show the feasibility of the logic elements. These JCCL devices, intended only for demonstration of the principles, have been operated at clock frequencies up to 5 MHz. Other properties of JCCL devices, such as silicon area used and possibility of applications in multivalued logic circuits make them look very promising. Calculations and experiments have shown that scaling down of the devices will allow clock frequencies of up to 50 MHz.