Title :
Long Retention of Gain-Cell Dynamic Random Access Memory With Undoped Memory Node
Author :
Nishiguchi, Katsuhiko ; Fujiwara, Akira ; Ono, Yukinori ; Inokawa, Hiroshi ; Takahashi, Yasuo
Author_Institution :
NTT Basic Res. Labs., Kanagawa
Abstract :
Low current leakage characteristics of a novel silicon-on-insulator (SOI) device are investigated in view of application to a gain-cell dynamic random access memory (DRAM). The device consists of a two-layered poly-Si gate. Since, in this device, the memory node is electrically formed by the gate in undoped SOI wire, no p-n junction is required. The retention is found to be dominated by the subthreshold leakage, which leads to long data retention. The device also achieved a fast (10 ns) writing time and its fabrication process is compatible with those of SOI MOSFETs. The present results, thus, strongly suggest a way of conducting a gain-cell DRAM to be embedded into logic circuits
Keywords :
DRAM chips; MOSFET; leakage currents; silicon-on-insulator; DRAM; MOSFET; gain-cell dynamic random access memory; logic circuits; low current leakage characteristics; silicon-on-insulator device; subthreshold leakage; undoped memory node; DRAM chips; Fabrication; Logic circuits; MOSFETs; P-n junctions; Random access memory; Silicon on insulator technology; Subthreshold current; Wire; Writing; Gain-cell dynamic random access memory (DRAM); long data retention; two-layered gate; undoped silicon-on-insulator (SOI) MOSFET;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2006.887625
